1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and, more specifically, to a technique for expanding the operating voltage of a semiconductor integrated circuit such as a microcomputer having a built-in EEPROM.
2. Description of the Related Art
Referring to FIGS. 7-13, the configuration and operation of an EEPROM and its peripheral circuits will be described first taking a microcomputer having a built-in EEPROM as an example.
FIG. 7 is a block diagram illustrating a general configuration of a microcomputer having a built-in EEPROM (Electrically Erasable Programmable Read Only Memory) for use in an IC card. In FIG. 7, reference numeral 10 denotes an IC card or a microcomputer for performing data processing. In the microcomputer 10, reference numeral 1 denotes a CPU or a central processing unit that is responsible for operations and control of data processing. That is, the CPU 1 is responsible for execution and control of a program associated with the data processing. Reference numeral 4 denotes a ROM serving as a program memory for storing a program required for the data processing. That is, the ROM 4 stores a program that executes various functions a user of a card needs. Reference numeral 5 denotes an EEPROM acting as a nonvolatile memory in which personal information of a card user is written and stored. Reference numeral 6 denotes a RAM acting as a temporary memory for temporarily storing data required for the data processing. Reference numeral 7 denotes an input/output circuit for inputting and outputting data from or to peripheral devices. Reference numeral 2 denotes a system bus for making connection between the above-described component elements. Furthermore, P1 denotes a positive power supply terminal, P2 a negative power supply terminal or a ground terminal, P3 a reset input terminal for receiving a reset signal to initialize the CPU 1, P4 a clock input terminal for receiving a clock signal, and P5 an I/O terminal for inputting and outputting data. The I/O terminal P5 is connected to the input/output circuit 7 that is further connected to the system bus 2. The input/output circuit 7 is responsible for data communication via the I/O terminal P5 between the IC card 10 and peripheral devices (not shown).
FIG. 8 is a block diagram illustrating a general configuration of an EEPROM. In this figure, reference numeral 31 denotes a memory cell array comprising memory cells (refer to FIGS. 9 and 10) arranged in a matrix form, in which memory cells on each row are connected in common to a corresponding word line and memory cells on each column are connected in common to a corresponding bit line (refer to FIG. 10 for both word and bit lines). Reference numerals 2a and 2b denote data buses included in the system bus. Selection of word lines is accomplished by a row decoder 32, and selection of bit lines is accomplished by a column decoder 33. The row decoder 32 sets one word line to an H level and sets the other word lines to an L level according to a row address Ar obtained via an address latch 34. The column decoder 33 selectively turns on a Y-gate 35 according to a column address Ac obtained via the address latch 34 so as to electrically connect a bit line to a write buffer 36. The row decoder 32 and the column decoder 33 are enabled or disabled by a controller 37. The address latch 34 latches an address signal in response to the output from the controller 37, and provides a row address Ar and a column address Ac to the row decoder 32 and the column decoder, respectively.
The controller 37 sets a time width or a pulse duration of a specific signal by using a timer 38. The controller 37 is also responsible for control regarding activation and inactivation of an oscillator 45, a Vpp generator 44, a column latch 39, Vpp switches 40, 46, a sense amplifier 41, the row decoder 32, and the column decoder 33. The controller 37 latches data, that should be written, in the latch 43 according to a control clock signal .PHI. and a write signal WR, and further provides the data to the write buffer 36.
When enabled, the column latch 39 temporarily holds write data given on each bit line. The Vpp switches 40 and 46, when enabled, raise the potentials of a bit line and a control gate line (refer to FIG. 10) connected to the column latch 39, and a word line connected to the row decoder 32 to a high voltage of Vpp. The sense amplifier 41, when enabled, amplifies data that has been stored via the y-gate 35 in a memory cell of the memory cell array 31, and provides the amplified data to an output buffer 42. The output buffer 42, in response to the output from the controller 37, outputs the data that is read out by the sense amplifier 41 onto the data bus 2b as read-out data. The controller 37 controls the address latch 34 and the output buffer 42, according to the control clock signal .PHI. and the read-out signal RD.
FIGS. 9A and 9B illustrate one memory cell included in the memory cell array 31 of the EEPROM shown in FIG. 8, wherein FIG. 9A illustrates its cross-section and FIG. 9B illustrates an equivalent circuit of the cell shown in FIG. 9A. As can be seen from these figures, a memory cell comprises a memory transistor MQ and a selection transistor SQ. As shown in FIG. 9A, n.sup.+ -diffusion regions 21-23 are formed in a p-type semiconductor substrate 20 by diffusing n-type impurities selectively into the semiconductor substrate 20. Reference numeral 29 denotes an insulating layer. A gate 24 is formed above the area between the n.sup.+ -diffusion regions 21 and 23 via an oxide film 47, and a floating gate 25 is formed above a part of n.sup.+ -diffusion region 22 and above the area between the n.sup.+ -diffusion regions 22 and 23 via an oxide film 48. The floating gate 25 has, above the n.sup.+ -diffusion region 22, a portion which is lower than the other portions. The portion of the oxide film 48 disposed under this lower portion of the floating gate 25 is as thin as 100 .ANG. and acts as a tunnelling oxide film 48a. A control gate 26 corresponding to the floating gate 25 is formed above the floating gate 25 via an oxide film 49. A bit line 28 made of an aluminum interconnection layer is also formed above the n.sup.+ -diffusion region 21.
The memory cell having the above-described structure comprises a series connection of an enhancement-type selection transistor SQ and a memory transistor MQ having a variable threshold voltage, as shown in FIG. 9B. The selection transistor SQ has a gate 24, and utilizes n.sup.+ -diffusion regions 21 and 22 as drain and source regions, respectively. The memory transistor MQ has a floating gate 25 and a control gate 26, and utilizes n.sup.+ -diffusion regions 22 and 23 as drain and source regions, respectively.
Writing into the memory transistor MQ is done basically by applying a high voltage to either the drain 22 or the control gate 26, and grounding the other, so as to induce an electric field as high as 10 MV/cm in the tunnelling oxide film 48a, thereby injecting or emitting electrons into or from the floating gate 25. If electrons are injected into the floating gate 25 of the memory transistor MQ, then its threshold voltage shifts in the positive direction. If electrons are extracted from the floating gate 25, then the threshold voltage shifts in the negative direction. Nonvolatile writing is accomplished by using correspondence between positive and negative threshold voltages as information "1" and "0".
Information is basically read out from the memory transistor MQ as follows. An H-level signal is applied to the gate 24 of a selection transistor SQ of a selected memory cell, and the source 23 of the memory transistor MQ is made a ground potential. Furthermore, a read-out voltage VCG having a magnitude, for example, of about 0V is applied to the control gate 26. In this situation, if the threshold voltage of the memory transistor MQ is positive, then the memory transistor MQ turns off. If the threshold voltage is negative then the memory transistor MQ turns on. If the memory transistor MQ turns on, a current flows from the bit line 28 toward the ground level via the selection transistor SQ and via the memory transistor MQ. This current is converted into a voltage and detected by a sense amplifier 41 (refer to FIG. 8) connected to the bit line 28. Thus, information has been read out. An L-level signal is applied to gates of selection transistors SQ of all non-selected memory cells so that all these selection transistors SQ are turned off. Therefore, in this case, there is no current flowing from the bit line 28 to the ground level, even if memory transistors MQ have a negative threshold voltage.
FIG. 10 illustrates a peripheral circuit of the memory cell array 31 of the EEPROM shown in FIG. 8. For simplicity, only four memory cells MC1, MC2, MC3, and MC4 organized in 1-byte 1-bit fashion are shown in the figure. In the following description, signal lines and signals transmitted through these lines are denoted by the same notations. The memory cells MC1-MC4, as shown in FIG. 9, comprise memory transistors MQ1, MQ2, MQ3, MQ4 and selection transistors SQ1, SQ2, SQ3, SQ4, respectively. The drains of the selection transistors SQ1 and SQ2 are connected to a bit line BL1, and the drains of the selection transistors SQ3 and SQ4 are connected to a bit line BL2. The sources of the memory transistors MQ1 and MQ2 are connected to a source line SL1, and the sources of the memory transistors MQ3 and MQ4 are connected to a source line SL2.
These source lines SL1 and SL2 are grounded via transistors T51 and T52 whose gates are supplied with an inverted program cycle selection signal PRS. The control gates of the memory transistors MQ1 and MQ2 are connected to a control gate line CGL1 via byte selection transistors T1 and T2, respectively. Similarly, the control gates of the memory transistors MQ3 and MQ4 are connected to a control gate line CGL2 via byte selection transistors T3 and T4, respectively. The gates of the transistors T1, T3, and the gates of the selection transistors SQ1, SQ3 are all connected to a word line WL1. The gates of the transistors T2, T4, and the gates of the selection transistors SQ2, SQ4 are all connected to a word line WL2. One end of the word line WL1 and that of WL2 are connected to the row decoder 32 via high voltage isolation transistors T5 and T6, respectively, wherein a power supply voltage Vcc is applied to the gates of the high voltage isolation transistors T5 and T6.
One end of each of the bit lines BL1, BL2 and one end of each of the control gate lines CGL1, CGL2 are connected to column latches 39a, 39b, 39c, 39d, respectively, via transistors T7, T8, T9, and T10, respectively. The other ends of the control gate lines CGL1 and CGL2 are connected to a common control gate line CCGL via transistors T61 and T62, respectively. The other ends of the bit lines BL1 and BL2 are connected to an input/output line I/O via Y-gate transistors T71 and T72, respectively. The gates of the transistors T61 and T71 are connected to an output line CDL1 of the column decoder 33. Similarly, the gates of the transistors T62 and T72 are connected to an output line CDL2. The common control gate line CCGL is connected to a buffer BF1, and the input/output line I/O is connected to a write buffer 36 and to the sense amplifier 41. The control gate lines CGL1, CGL2, the bit lines BL1, BL2, and the word lines WL1, WL2 are connected to Vpp switches 40a-40d, 46e, 46f, respectively. The Vpp switches 40a-40d, 46e, 46f are connected to a high voltage line VPPL via which a high voltage of 15-20V is supplied. In response to an applied erase clock signal CLKE, program clock signal CLKP, and word line clock signal CLKW, the Vpp switches 40a-40d, 46e, 46f raise the connected control gate lines CGL1, CGL2, bit lines BL1, BL2, and word lines WL1, WL2 up to the high voltage Vpp if these lines are at an H level. When the word lines WL1 and WL2 are raised to the high voltage Vpp, the row decoder 32 is isolated from the high voltage Vpp by the transistors T5 and T6 whose gates are supplied with the supply voltage Vcc.
A bit signal transfer control signal BTTR is connected to the gates of the transistors T7 and T8, and a control gate signal transfer control signal CGTR is connected to the gates of the transistors T9 and T10. When these signals are at H levels, mutual signal communications are accomplished between the bit lines BL1, BL2, control gate lines CGL1, CGL2, and the column latches 39a, 39b, 39c, 39d. When the bit lines BL1, BL2, and the control gate lines CGL1, CGL2 are raised to the high voltage Vpp, the column latches 39a, 39b, 39c, 39d are isolated from the high voltage Vpp, since the gates of the transistors T7-T10 are at the Vcc level.
The transistors T11 and T12 are connected to the control gate lines CGL1 and CGL2, respectively, and the gates of the transistors T11 and T12 are connected to a control gate line reset signal CGRST. When the control gate line reset signal CGRST rises to an H level, the control gate lines CGL1 and CGL2 falls to an L level. The bit lines BL1 and BL2 are connected to transistor T13 and T14, respectively, and the gates of the transistors T13 and T14 are connected to a bit line reset signal BTRST. When the bit line reset signal BTRST rises to an H level, the bit lines BL1 and BL2 fall to an L level. The bit lines BL1 and BL2 are also connected to transistors T15 and T17, respectively. The transistors T15 and T17 are connected to transistors T16 and T18 respectively. The gates of the transistors T15 and T17 are connected to the column latches 39a and 39b, respectively. The gates of the transistors T16 and T18 are connected to a precharge signal PRCH. When the column latches 39a and 39b are at an H level, if the precharge signal PRCH rises up to an H level, then both bit lines BL1 and BL2 rise to an H level.
The inverted program cycle selection signal PRS, the control gate line reset signal CGRST, the bit line reset signal BTRST, the control gate signal transfer control signal CGTR, the bit signal transfer control signal BTTR, and the precharge signal PRCH are driven by buffers BF2, BF3, BF4, BF5, BF6, and BF7, respectively.
Referring to FIGS. 8 and 10, read-out operation of the EEPROM will be described below. First, selections of word lines WL, control gate lines CGL, and bit lines BL are performed by the row decoder 32 and the column decoder 33. In the following description, an operation will be explained for the case where a memory cell MC1 is selected by selecting the word line WL1 and by turning on the transistors T61 and T71 so as to select the control gate line CGL1 and the bit line BL1. The inverted program cycle selection signal PRS is raised to an H level, and the source lines SL1 and SL2 are grounded. Furthermore, the controller 37 disables the column latches 39a-39d, the Vpp switches 40a-40d, 46e, 46f, and the write buffer 36. The buffer BF1 supplies a voltage of 0V to the gate of the memory transistor MQ1 via the common control gate line CCGL, transistor T61, and transistor T1. Then, if the memory transistor MQ1 has a positive threshold voltage the memory transistor MQ1 turns off. If the threshold voltage is negative, the transistor MQ1 turns on. The presence or absence of a current flowing through the bit line BL1 due to the turning on or off of the memory transistor MQ1 is detected from the change in the potential on the input/output line I/O by the sense amplifier 41. The potential change detected by the sense amplifier 41 is further amplified, and provided as a read-out output signal. In this way, the read-out operation is performed.
FIG. 11 is a timing chart illustrating various signal waveforms relating to a writing operation of the EEPROM. Referring to FIGS. 8-11, a writing operation will be explained below for the case where the memory cell MC1 is selected. First, a latch cycle starts with a latch starting signal WE to drive a latch signal LATCH to an H level. When the latch cycle starts, the controller 37 enables the column latches 39a-39d, the column decoder 33, and the write buffer 36, and the common control gate line CCGL is set to an H level. On the other hand, the controller 37 disables the row decoder 32 and the sense amplifier 47. In a time period during which the latch signal LATCH is kept at the H level, the transistors T61 and T71, selected by the column decoder 33, turn on, and the data ("H" corresponds to information "O", and "L" corresponds to information "1") held by the data latch 43 is latched by the column latch 39a via the write buffer 36, the input/output line I/O, the bit line BL1, and the transistor T7. Furthermore, an H level is latched by the column latch 39c via the common control gate line CCGL and the control gate line CGL1. Then, once a write starting signal goes to an H level, the signal LATCH changes to an L level, and an erase cycle signal ERS rises, whereby an erase cycle starts. An erasing cycle is such a cycle during which the erasing cycle signal ERS is at an H level, and a program cycle is such a cycle during which the program cycle selection signal PRS (that is an inverted signal of the inverted program cycle selection signal PRS) is at an H level. The H-level pulse durations of these signals ERS and PRS are set to proper values by the controller 37 by using the timer 38.
During the erasing cycle, the row decoder 32 is enabled by the controller 37, and only the word line WL1 is set to an H level by the row decoder 32. Furthermore, the column decoder 33 is disabled by the controller 37. A high voltage Vpp having a pulse duration of about 4 msec is then applied on the high voltage line VPPL thereby applying the high voltage Vpp to the Vpp switches 40a-40d, 463, 46f. Then, the controller 37 makes a high frequency oscillator, which comprises an oscillating circuit 45 and a Vpp generator 44, generate a high frequency erase clock signal CLKE and a word line clock signal CLKW having a frequency of a few MHz, which are supplied to the Vpp switches 40a, 40b, and the Vpp switches 46e, 46f, respectively. Since the inverted program cycle selection signal PRS is at the H level, the source lines SL1 and SL2 are grounded. In the above-described state, the word line WL1 and the control gate line CGL1 are raised to the high voltage Vpp by the Vpp switches 40a and 46e, respectively. As a result, tunneling occurs between the floating gate 25 (refer to FIG. 9) and the drain region (n.sup.+ -diffusion region 22) of the memory transistor MQ1, whereby electrons are injected into the floating gate 25. As a result, the threshold voltage of the memory transistor MQ1 shifts in the positive direction (information "1" is stored). When the erasing cycle is complete, the potential of the control gate line CGL1 is reset to an L level.
The erasing cycle signal ERS then falls, and the precharge signal PRCH rises to an H level. Then, a program cycle starts with rising of the program cycle selection signal PRS. The controller 37 disables the word line clock signal CLKW and the erase clock signal CLKE. Subsequently, the controller 37 provides again a high frequency program clock signal CLKP and a word line clock signal CLKW having a frequency of a few MHz from the high frequency oscillator to the Vpp switches 40c, 40d, and the Vpp switches 46e, 46f, respectively. Since the inverted signal PRS is at an L level, the source line SL1 is in a floating state. In this situation, if an H level is latched by the column latch 39a, the word line WL1 and the bit line BL1 are raised to the high voltage Vpp. As a result, tunneling occurs between the floating gate 25 (refer to FIG. 9) and the drain region (n.sup.+ -diffusion region 22) of the memory transistor MQ1, whereby electrons are emitted from the floating gate 25. As a result, the threshold voltage of the memory transistor MQ1 shifts in the negative direction (information "0" is stored). On the other hand, in the case where an L level is latched by the column latch 39a, only word line WL1 rises up to the high voltage Vpp, and the threshold voltage of the memory transistor MQ1 is maintained unchanged. In this way, the writing operation is complete.
FIG. 12 is a circuit diagram illustrating the internal configuration of the Vpp generator (high voltage generator) 44 shown in FIG. 8, which will be described below.
The gate and the drain of a transistor M1 are connected to each other. A capacitor C1 is connected to the node at which the gate and the drain are connected. The source of the transistor M1 is connected to the drain of a transistor M2 disposed at the following stage. The gate and the drain of the transistor M2 are also connected to each other, and a capacitor C2 is also connected to the node which connects the gate and drain of the transistor M2. Clock signals CLK2 and CLK 1 are applied to the other ends of the capacitors C1 and C2 connected to the drains of the transistors M1 and M2, respectively, wherein the phases of the clock signals CLK2 and CLK1 are opposite each other. Several stages, each having a configuration similar to that described above, are cascaded. The drain of the transistor M1 at the first stage is connected to the source of the transistor M4. The drain of the transistor M4 is connected to the power supply voltage Vcc. The gate of the transistor M4 is controlled by the output signal provided by the controller 37. The charge pump output is provided via the source of the transistor M3 at the end stage. The high voltage Vpp is provided as the output of the Vpp generator 44, and applied to the Vpp switches 40a-40d, 46e, 46f via the high voltage line VPPL so as to raise the control gate lines CGL1, CGL2, the bit lines BL1, BL2, and the word lines WL1, WL2 up to the high voltage according to control signals. The transistor M7 discharges the high voltage Vpp in response to the signal provided by the controller 37.
The Vpp generator 44 also includes a waveform shaping circuit 200, which will be described later.
Now, the configuration of a high voltage switch shown in FIG. 10 will be described taking the high voltage switch 40c as an example. The other high voltage switches are configured in the same manner as that of the high voltage switch 40c, and thus these will not be described. The drain of a transistor M5 is connected to the high voltage, and its source is connected to the drain of a diode-connected transistor M6. The source of the transistor M5 is further connected to one end of a capacitor C4. The term "diode connection" refers to a configuration in which the gate and the drain of a transistor are connected to each other, forming a diode between the source and the drain. The source of the transistor M6 is connected to the gate of the transistor M5, and further connected to the bit line BL1. The other end of the capacitor C4 is connected to the program clock signal CLKP. Clock signals having the same phase are applied to the clock signal lines CLKP and CLK2. A clock signal having a phase opposite to those applied to lines CLKP and CLK2 is applied to the clock signal line CLK1 (refer to FIG. 12).
Operations of the Vpp generator 44 and of the high voltage switch 40c will be described below. In the Vpp generator 44 shown in FIG. 12, charges are stored in the capacitor C1 when the clock signal CLK2 is at an L level. When the clock signal CLK2 rises, the charges stored in the capacitor C1 are transferred to the capacitor C2 via the transistor M1. When the clock signal CLK2 then falls with the rising clock signal CLK1, charges are further stored in the capacitor C1. At this time, charges stored in the capacitor C2 are transferred to a capacitor of the following stage. In this operation step, no charges are transferred to the capacitor C1 since the transistor M2 acts as a diode. In this way, charges are sequentially transferred according to the clock signals CLK1 and CLK2, and finally, a raised voltage is output via the charge pump output.
In the high voltage switch 40c shown in FIG. 10, when the column latch 39a holds an H level and the signal BTTR is at an H level, the bit line BL1 rises. In this state, when the signal CLKP is at an L level, the transistor M5 turns on, whereby the capacitor C4 is charged by the high voltage Vpp until the transistor M5 turns off. As a result, the signal CLKP rises, whereby the charges stored in the capacitor C4 are transferred to the bit line BL1 via the transistor M6. As a result, the potential at the gate of the transistor M5 connected to the bit line BL1 rises, and thus the capacitor C4 is further charged by the high voltage until the transistor M5 turns off (the signal CLKP is at an L level, in this state). In this way, the operation is performed repeatedly, whereby the bit line BL1 can be raised to the high voltage Vpp according to the signal applied via the column latch 39a.
The other Vpp switches operate in the same manner as in the case of the high voltage switch 40c described above.
The clock signals CLK1, CLK2, CLKW, CLKE, and CLKP are generated based on the signal from the oscillator 45, the erase cycle signal ERS, and the program cycle selection signal PRS.
As described above, a high voltage is applied to the control gate or the drain of a memory transistor MQ via a selection transistor SQ. However, if the output of the high voltage (Vpp) switch is directly applied to the control gate 26 or the drain 22 of a memory transistor MQ, the small time constant associated with the rising waveform of the output of the high voltage Vpp, that is, the rapid rising of the high voltage Vpp causes great damage to the tunneling oxide film 48a. In the worst case, the tunnelling oxide 48a will break down. To avoid the above problem, there is provided a waveform shaping circuit in the Vpp generator 44, for properly setting the rising time constant to a rather large value thereby reducing the damage to the tunnelling oxide film 48a.
FIG. 12 also includes the waveform shaping circuit 200.
As shown in this figure, the output voltage Vpp of the Vpp generator 44 is divided by the capacitors C11 and C12, and the divided voltage is applied as a sample signal to the negative input of a comparator 220 via an interconnecting line L1. On the other hand, the positive input of the comparator 220 is connected to the output of the power supply voltage Vcc via a switched capacitor 210 and an interconnecting line L2.
The switched capacitor 210 comprises: transistors T211 and T212 connected in series between the power supply voltage Vcc and the interconnecting line L2; a capacitor C14 with one end connected to the node connecting the transistors T211 and T212 and the other end grounded; and a capacitor C13 connected between the interconnecting line L2 and ground. A clock signal .PHI. and an inverted clock signal .PHI. are applied to the gates of the transistors T211 and T212, respectively. The drain of the transistor T211 is connected to the power supply voltage Vcc. The source of the transistor T212 is connected to the interconnecting line L2.
With this arrangement, waveform shaping is performed on the rising voltage on the interconnecting line L4 according to a time constant determined by the clock signal .PHI. of the switched capacitor 210 and the capacitors C13 and 14. The waveform-shaped voltage is applied as a reference voltage to the positive input of the comparator 220.
The difference between this reference voltage and the output voltage of the above-described Vpp generator 44 is output as a feedback signal SF by the comparator 220. According to this feedback signal SF, the clock signals CLK1 and CLK2 are controlled so that the high voltage output of the Vpp generator 44 may rise up at a rate similar to that of the reference voltage.
FIG. 13 illustrates a configuration of a semiconductor substrate of a semiconductor integrated circuit for a microcomputer having a built-in EEPROM, according to a conventional technique. FIG. 13A schematically illustrates a layout of functional blocks on a semiconductor substrate, and FIG. 13B is a cross-sectional view of the semiconductor substrate of FIG. 13A taken along line 13B--13B. In this figure, reference numeral 100 denotes a p-type semiconductor substrate on which a semiconductor integrated circuit is formed. Reference numerals 101, 102, 103 denote a CPU, an ROM/RAM, and a UART or an input/output portion, respectively. Reference numerals 104 and 105 denote an EEPROM control system. Reference numerals 107 and 108 denote an EEPROM memory cell array, and an EEPROM peripheral high voltage system, respectively. Reference numerals 110, 111, 112 denote an n-well region, a p-type substrate region, a p-well region, respectively. Reference numeral 114 denotes a twin well region consisting of the n-well region 110 and the p-well region 112.
The EEPROM memory cell array 107 corresponds to the memory cell array 31 in FIG. 8, and to four portions each surrounded by a broken line in FIG. 10 wherein each portion comprises one memory cell MC and a transistor T. The EEPROM peripheral high voltage system 108 corresponds to elements of FIG. 8 including the Vpp switches 40, 46, the Y-gate 35, and a portion (a high voltage portion) of the Vpp generator 44. The EEPROM peripheral high voltage system 108 also corresponds to elements of FIG. 10 including the Vpp switches 40a-40d, the Vpp switches 46e, 46f, the transistors T5-T18, the transistors T51, T52, and the transistors T61, T62, T71, T72. The EEPROM peripheral high voltage system 108 also corresponds to elements of the Vpp generator 44 shown in FIG. 12, including the transistors M1-M4, M7, and the capacitors C1-C3, C11, C12. These corresponding portions of FIGS. 10 and 12 are each surrounded by an alternating long and short dash line 111a.
The EEPROM control systems 104 and 105 correspond to elements of FIG. 8 including the write buffer 36, the sense amplifier 41, the output buffer 42, the data latch 43, the column decoder 33, the row decoder 32, the address latch 34, the column latch 39, the controller 37, the timer 38, the oscillator 45, and the other portion of the Vpp generator 44. The EEPROM control systems 104 and 105 also correspond to elements of FIG. 10 including the write buffer 36, the sense amplifier 41, the buffers BF1-BF7, the column decoder 33, the row decoder 32, and the column latch 39a-39d. The EEPROM control systems 104 and 105 also correspond to the portion of the waveform shaping circuit 200 of FIG. 12 except for the capacitors C1 and C12.
Portions, which are not subjected to the application of the high voltage Vpp, in the CPU 101 the ROM/RAM 102, the UART 103, and the EEPROM control systems 104, 105 are formed with CMOS structures in twin well regions 114 each consisting of an n-well region 110 and a p-well region 112, as shown in FIG. 13A or 13B. On the other hand, elements to which the high voltage Vpp is applied such as the EEPROM memory cell array 107 and the EEPROM peripheral high voltage system 108, are formed with NMOS structures on the p-type substrate region 111. It is desirable that the p-type substrate region 111, in which the EEPROM memory cell array 107 and the EEPROM peripheral high voltage system 108 are formed, be surrounded by a p-well region as shown by the broken line 112a in FIG. 13A.
As described above, the region to which the high voltage Vpp is not applied is formed on the twin well region 114 consisting of the p-well region 112 and the n-well region 110 each formed in the p-type semiconductor substrate so that a high integration density may be obtained by the most advanced technology. Regions to which the high voltage Vpp is applied are formed, for example, with NMOS structures on the p-type substrate region 111 so that the substrate effects may be suppressed whereby the high voltage system may operate successfully. Furthermore, the p-type substrate region 111 is surrounded by the p-well region so as to enhance the resistance to latchup so that latchup effects may be suppressed.
In the above description, a conventional technique of a semiconductor integrated circuit for a microcomputer having a built-in EEPROM has been discussed. However, for example in the Vpp switch 40c shown in FIG. 10, when the high voltage Vpp is selectively supplied to a memory cell, it is required that the amplitude of the clock signal should be greater than the sum of the threshold voltage Vth of the transistor M5 which is responsible for the selection of the memory cell and the threshold voltage Vth of the transistor M6 forming the charge pump. If this condition is not met, the high voltage Vpp does not appear at the output. Since the amplitude of the clock signal is determined by the power supply voltage Vcc, if the power supply voltage Vcc decreases, it becomes impossible to transfer the high voltage Vpp to the output. The threshold voltage Vth increases as the source voltage increases. Therefore, it will become more difficult to transfer the high voltage to the output as the output increases. For these reasons, the Vpp switch (high voltage switch) causes difficulty in reduction of the operating voltage of a semiconductor integrated circuit.
In the Vpp generator, the charge pump output of the Vpp generator is applied to the input of the waveform shaping circuit. However, there is a slight difference in voltage waveform between the charge pump output and the actual output of the Vpp switch. In this sense, the waveform shaping is not accurate. Especially when the Vpp switch has a high capability, the difference in voltage between the charge pump output and the actual output of the Vpp switch becomes great.